The present invention relates to the field of electronic design automation (EDA) software, and more specifically, to techniques of checking and verifying the quality of optical proximity correction (OPC) data for an integrated circuit design.
Integrated circuit technology is a marvel of the modem age. Integrated circuits are used in many applications such as computers, consumer electronics, networking, and telecommunications. There are many types of integrated circuits including microprocessors, microcontrollers, application specific integrated circuits (ASICs), gate arrays, programmable logic devices (PLDs), field programmable gate arrays (FPGAs), dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read only memories (EPROMs), electrically erasable programmable read only memories (EEPROMs), and Flash memories. Integrated circuits (ICs) are also sometimes referred to as “chips.”
Integrated circuit technology continues to rapidly advance. As feature sizes become smaller and smaller, the process window gets narrower, and the design rule complexity increases. Optical and other processing effects become more pronounced and dramatically reduce the yield of good dies per wafer. Layout feature induced yield loss is becoming a dominant factor in 0.18 micron and smaller technology (such as 0.15, 0.13, and 0.09 micron technologies) in subwavelength designs.
Optical proximity effects cause defects such as transistor poly pull-back, channel length shortening and nonuniformity, pattern scum, low contrast, and other processing problems. Because of these optical proximity effects, the patterns drawn on a mask are not what results on the wafer after processing: in other words, what you see is not what you get. In order to increase the yield, one approach to address the problem is to use shorter wavelength light, such as X-rays, for lithography. However, it may be some years before X-ray lithography becomes production ready. Another approach is to adjust the mask data to compensate for the proximity effects using an optical proximity correction treatment. Optical proximity correction is a technique of predistorting layout mask patterns such that the printed silicon patterns are as close to the desired shapes as possible. Optical proximity correction treatment is typically done by a foundry on the mask data using optical proximity correction tools from some EDA software vendors.
However optical proximity correction treatment cannot guarantee the one hundred percent correctness of layout shape distortion due to some correction constraints. For example, there are mask-making constraints. Mask-making is a mechanical process and has limits in space or distance control, or both. Also a generic optical proximity correction treatment may not correct some design specific patterns. Manual involvement in optical proximity correction is needed in this case to further improve the production yield. Therefore optical proximity correction treatment result (also referred as optical proximity correction data in the following discussion) verification is needed. The verification report can be used either to guide the local refinement by the optical proximity correction treatment process or to guide the layout design refinement.
In this patent application, the integrated circuit layout design data before optical proximity correction treatment is referred to as pre-optical proximity correction data and the layout data after optical proximity correction treatment is referred to as post-optical proximity correction data. Both pre-optical proximity correction data and post-optical proximity correction data are represented in the industry standard GDSII format.
It is important to provide automation tools to simplify and expedite the task of addressing the proximity effects problem. It is desirable to evaluate and check optical proximity correction data to identify vulnerable layout drawing patterns of a design. It is important that the automation tool provide accurate and fast results, especially when operating on a full-chip scale. As can be seen, techniques are needed to inspect and verify the quality of optical proximity correction data of an integrated circuit.